Microelectronic devices used in fabricating integrated circuits are manufactured by employing photolithographic techniques. Fabricating various structures, particularly electronic device structures, typically involves depositing at least one layer of a photosensitive material, generally known as a photoresist material on a substrate. The photoresist material may then be patterned by exposing it to radiation of a certain wavelength to alter characteristics of the photoresist material. In many instances, the radiation is from ultraviolet range of wavelengths causing desired photochemical reactions to occur within the photoresist. The photochemical reactions typically change the solubility characteristics of the photoresist, thereby permitting removal of certain selected portions of the photoresist while maintaining the other portions of the photoresist on the substrate. The selective removal of certain parts of the photoresist allows for protection of certain areas of the substrate while exposing other areas. The portions of the photoresist that remain on the substrate are used as a mask or stencil for processing the underlying substrate.
As methods for producing miniature electronic structures improve, the desire to produce even smaller structures has continued to increase. For instance, the reduction of the FET dimensions has been the primary vehicle pursued to meet the insatiable consumer need for faster electronics. A first-order correlation to faster FET is smaller gate width dimension, and therefore it is called the Critical Dimension (CD). FIG. 1 shows a simple cross-sectional schematic of an FET. Thin dielectric 5 is between substrate 1 and gate electrode 4. Source 2 and drain 3 are doped regions to the sides of gate electrode 4. The width of the gate is CD 6. It is generally known to those skilled in the art that as the CD gets smaller, the FET gets faster.
The dimension of most key features in microelectronics is limited by the dimension of the resist that is printed in a photolithography step. Therefore, the primary focus for producing smaller CDs has been upon improved photolithography. FIGS. 2a-2d shows a most common manufacturing process used to create a FET. A stack of films is deposited on wafer or substrate 110 as illustrated in FIG. 2a. First, thin dielectric 112, usually a thermal oxide (Tox), is grown on substrate 110. Then gate material 114 is deposited, which is usually polysilicon. Then photoresist 116 is spun on. FIG. 2b shows the lithography process. Photoresist 116 is exposed to light energy through a mask, and when washed with a developer, desired pattern 122 remains. This pattern exposes the layer underneath to the gate electrode etch process as shown in FIG. 2c. Usually, this etch process is a RIE (Reactive Ion Etch) which removes the exposed layer, yet keeps the features under the photoresist mask. Finally, the photoresist is removed and only desired gate electrode 114 remains. The width of photoresist 122 was transferred directly to gate electrode 114, minus etch-bias 118 from the RIE. Etch-bias 118 is the difference between initial photoresist CD 122 and final gate electrode CD 142 as shown in FIG. 2d. 
Different etching processes and compositions can produce more or less etch-bias. A larger etch-bias produces smaller gate CDs. However, there is typically a cost associated with this desired result. Some compositions will produce large N-I (nested to isolated linewidth) offset deltas when the etch-bias is too high. Other compositions will produce undesirable sidewall profiles. A major problem of the RIE aggressively going after a large etch-bias is the complete removal of the photoresist mask during the etch. This results in “opens” or removal of the polysilicon gate feature completely in a localized or general area.
Another method for defining gate electrodes is with a hard mask process. FIGS. 3a-3d show that this method simply inserts material 313 which is usually a dielectric, between photoresist 116 and gate material 114. This requires an extra etch step to etch material 313 using photoresist 116 as the soft mask. Hard mask gate definition is often used to enhance polysilicon gate profile and decrease aspect ratio so that removing bottom corner of gate material 114 is easier. However, the same problems described above for the soft mask (photoresist) method exist for the hard mask method when etch-bias is aggressively pursued in order to achieve sub-lithographic features.
One particular current technique for achieving sub-lithographic gate CD involves a separate photoresist trimming step. Here, the “as printed” photoresist is consumed by an oxygen plasma prior to RIE etching. However, there is a limit to how much the resist can be trimmed and the resist retain acceptable profiles. Projected manufacturing demands for smaller linewidths cannot be met by current photo and RIE trim capabilities.
One key process which has been developed is a trim process using a vapor phase etch (VPE) process as described in commonly assigned pending application, Ser. No. 09/727,139, “Etching of Hard Masks” by Cantell et al., filed on Nov. 30, 2000, herein incorporated by reference. The VPE process described by Cantell et al. is a self-limiting etch and has very little to no N-I linewidth offset deltas which produces uniformities less than about 1%, 1 sigma. In addition, the VPE process is insensitive to pattern loading; that is, the same amount of etch removal is done on each line independent of the number of lines per unit area (pattern loading). Whether within a chip or within a wafer, the same amount of etch removal occurs on all lines that are exposed to the VPE process independent of pattern loading. However, the VPE process described by Cantell et al. does not address preserving the initial thickness of the hard mask that is deposited. With the resist removed, the thickness of the hard mask is thinned down by the VPE process thereby requiring a thicker initial thickness for the hard mask. A thicker hard mask would require a longer etch time during the hard mask definition step where photoresist is used as the soft mask, thus increasing erosion of the photoresist and adversely affecting the profile of the hard mask. In many instances, limitations on photoresist thickness prohibit increasing the photoresist thickness to compensate for the longer hard mask etch time.
Not only is it desired to achieve small CDs, it is important to minimize the non-uniformity in CDs across a wafer or across a chip. Differences in topography can contribute to differences in resist thickness which in turn contribute to non-uniformities in the resist linewidth. Generally, the top and bottom surfaces of the resist layer are in contact with materials which have a different index of refraction than the resist. These index of refraction differences give rise to light reflections at each interface. At certain resist thicknesses there can be constructive or destructive interference between the various reflected light waves giving rise to a light intensity within the resist which depends on resist thickness. These differences in light intensity result in differences in CD of the developed resist line.
Generally, the reflections are minimized by placing an anti-reflective coating (ARC) between the resist and the underlying substrate. Most organic and some inorganic ARCs operate by absorbing incident light. Essentially all inorganic ARCs require careful control of the composition of the inorganic layer. The type which absorbs incident light must match the index of refraction of the ARC at the resist interface to the index of refraction of the resist to minimize reflections at the interface. In another type, the index of refraction, light absorbency, and thickness are all controlled to minimize reflection. If the underlying material or resist index of refraction changes, then the composition and thickness of this type of ARC must be changed and redeveloped.
As the demand for smaller and more uniform CDs continues, there is a need for new methodologies to produce such smaller and more uniform CDs. Achieving smaller photoresist CDs has proved very difficult as the current technology is at the end of the UV spectrum. Other methods for producing sub-lithographic features are desired. Bearing in mind these demands and deficiencies of the prior art, it would therefore be desirable to provide an improved method of forming a semiconductor device.